Processor Design

Execution Stages

Store/type	Data Processing	Load	Store	Branch
1 - fetch	ADD r2, r0, r1	LDR r1, [r0, #4]	STR r1, [r0, #4]	BEQ [PC, #16]
2 - reg read	r0, r1	r0	r0, r1	PC
3 - use ALU	[r0] + [r1]	[r0] + 4	[r0] + 4	[PC] + 16
4 - use mem	-	read	write	-
5 - reg write	r2<-	r1<-	-	if z == 1 PC <-

Data path stage 1

Data path stage 2

Data path stage 3

Data path stage 4

Data path stage 5

registers are clocked, output always on
data flow controlled by asserting register input and mux select signals (if not listed, control sig deasserted if listed, asserted)

e.g. ADD r2, r0, r1

e.g. LDR r1, [r0, #4]

Stage	Action	Control Signals Asserted
1 - fetch	MAR <- [PC]	MAR in, MAR_sel = PC
	read memory	read
	IR <- mem data in	IR_in, MDR_sel = mem
	PC <- [PC] + 4	PC_sel = inc, PC_in
2 - reg read	RA <- [r0]	rd A = 0, RA_in
3 - ALU	RZ <- [RA] + 4	A_sel = A, B_sel = offset, ALU_op = add, Z_in
4 - mem	MAR <- [RZ]	MAR_sel = Z, MAR_in
	read memory	read
	RY <- mem data in	Y_sel = mem, RY_in
5 - reg wr	r2 <- [RY]	wrC = 1, wrEn

e.g. STR r1, [r0, #4]

Stage	Action	Control Signals Asserted
1 - fetch	MAR <- [PC]	MAR in, MAR_sel = PC
	read memory	read
	IR <- mem data in	IR_in, MDR_sel = mem
	PC <- [PC] + 4	PC_sel = inc, PC_in
2 - reg read	RA <- [r0]	rd A = 0, RA_in
	RB <- [r1]	rd B = 1, RB_in
3 - ALU	RZ <- [RA] + 4	A_sel = A, B_sel = offset, ALU_op = add, Z_in
4 - mem	MAR <- [RZ]	MAR_sel = Z, MAR_in
	MDR <- [RB]	MDR_in
	write memory	write
	RY <- mem data in	Y_sel = mem, RY_in
5 - reg wr	-	-

e.g. BEQ [PC, #16]

Stage	Action	Control Signals Asserted
1 - fetch	MAR <- [PC]	MAR in, MAR_sel = PC
	read memory	read
	IR <- mem data in	IR_in, MDR_sel = mem
	PC <- [PC] + 4	PC_sel = inc, PC_in
2 - reg read	-	-
3 - ALU	RZ <- [PC] + 16	A_sel = A, B_sel = offset, ALU_op = add, Z_in
4 - mem	RY <- [RZ]	Y_sel = Z, RY_in
5 - reg wr	if (z == 1), PC <- [RY]	PC_sel = Y, PC_in = (Z == 1)

WMFC = wait for memory function complete
MFC = memory function complete(from memory)
asserting WMFC with read or write control signal stalls step counter until memory asserts MFC(i.e. waits for read/write to finish)
Combinational logic
inputs: control step, instruction, condition flags
outputs: all control signals

e.g. IR_in = T1

PC_in = T1 + T5 (Z flag == 1) BEQ

PC_sel = T1

PC _sel = T5

read = T1 + T4 LDR write = T4 STR

WMFC = read + write